This invention relates in general to the field of digital logic circuitry and, in particular, to current mode logic full adders.
Current mode logic allows soft saturation mode operation for fast response times. The collector-base junction may be allowed to be partially forward-biased. Even though the junction is forward biased, no minority carrier injection takes place (hard saturation implies injection). Therefore, no speed degradation occurs. Hard saturation conditions are not allowed and are eliminated by appropriately level shifting an input signal to a base of a transistor so that the collector-base junction is not fully forward biased.
A number of transistor connection structures can be employed as logical operators. An emitter follower can be used as voltage level shifter, as can a transistor with collector shorted to base providing a voltage level drop of a diode ("on" voltage). Two transistor collectors connected within a gate (i.e., a single current source circuit) can function as a logical "OR." Two transistor collectors connected across gates can function as a logical "AND."
Various arithmetic logic units, including current mode logic units, are known in the prior art. There are two basic schemes to handle multiple bit additions with carries. The first is a carry look ahead, which generates the carry output in parallel with the sum output of individual adders. The second is a ripple carry, which is a serial configuration in which the carry of the first bit is input to the second bit and is used for the calculation of the final carry out result. The second configuration is commonly used in high-performance multipliers.
Standard multi-bit adders are typically based on the carry look ahead scheme to maximize speed, i.e. to eliminate the propagation delays of ripple carry adders. The use of the carry look ahead configuration requires increased gate current and additional complexity in component number and size, however. Carry look ahead configurations also may require clamping diode action in controlling more than one current input to one logic level. For a sufficiently efficient design adding a small number of bits, the ripple carry can be less complex, be easier to fabricate, and require less power than the carry look ahead scheme, without sacrificing throughput.